1. Field of Invention
The present invention relates to non-volatile semiconductor memories, and more particularly to a memory cell array of a multi-bit non-volatile memory device configured to store multi-state bit information in each memory cell thereof. The present invention also relates to a method for driving such a multi-bit non-volatile memory device.
2. Description of the Related Art
Generally, non-volatile semiconductor memories are mainly classified into a mask ROM, an EPROM, an EEPROM, and a flash-EEPROM. In particular, EEPROM's have recently been highlighted as a permanent memory for personal notebook computers or as a recording medium for portable terminal devices such as digital cameras and memory cards because they have characteristics capable of electrically converting information and flash-erasing stored data while consuming a small amount of electric power.
In such typical non-volatile semiconductor memories, memory cells thereof can maintain only one of two information storage states, namely, "ON" and "OFF" states. The ON or OFF state of each memory cell defines information of one bit. Accordingly, where a memory device is required to store data of N (N is a natural number not less than 2) bits, it requires N independent memory cells. When an increase in the number of bits of data to be stored in a memory device consisting of one-bit memory cells is required, the number of the memory cells should increase correspondingly. Information stored in each one-bit memory cell is determined in accordance with a programmed status of the memory cell. The information storage states of memory cells are determined in accordance with a difference in threshold voltage among the memory cells (the threshold voltage is a minimum voltage to be applied between the gate and source of a cell transistor included in each memory cell in order to switch the cell transistor to its ON state). In mask ROM's, such a difference in threshold voltage is appropriately programmed using an ion implantation technique in the fabrication of the devices.
On the other hand, in the case of EPROM's, EEPROM's or flash-EEPROM's, a difference in threshold voltage among memory cells is obtained by storing floating gates, respectively included in the memory cells, with different amounts of charge. Generally, each memory cell transistor has two gates disposed over a drain-source channel region. The upper gate is called the "control gate". A charge storage layer is surrounded by an insulating material between the control gate and channel region. This charge storage layer is called the "floating gate". As the amounts of charge stored in floating gates of memory cells differ from one another, as mentioned above, the threshold voltage of the memory cells also differ from one another. Accordingly, the states of information stored in the memory cells are distinguished from one another. In this regard, when the information stored in the cell is to be read, it is necessary to check the programmed information storage status of the memory cell. To this end, signals required to select a desired memory cell and to read information stored in the memory cell are applied to the circuits associated with the memory cell using a decoder circuit. As a result, a current or voltage signal corresponding to the information storage status of the memory cell is obtained on a bit line associated with the memory cell. Accordingly, it is possible to determine the status of the information stored in the memory cell by measuring the obtained current or voltage signal.
Memory cell array configurations of such memory devices are mainly classified into a NOR type and a NAND type. In the case of NOR-type cell arrays, each memory cell is coupled between a bit line and a ground line. In the case of NAND-type cell arrays, a plurality of memory cells are connected in series between a bit line and a ground line. In the technical field, memory cells, which are connected in series to a bit line, along with select transistors (each select transistor is arranged between a corresponding memory cell and the associated bit line, or between each memory cell and the associated ground line) constitute a string. In the case of a NAND-type memory device, which has a greater density than NOR-type memory devices, the select transistors included in a selected string must be in an ON state when the status of information stored in the memory device is to be read. In this case, the control gates of memory cells unselected in the selected string are supplied with a voltage higher than the voltage applied to the control gates of selected memory cells. As a result, the unselected memory cells exhibit an equivalent resistance value lower than that exhibited in the selected memory cells. Therefore, current flowing through the selected string from the associated bit line depends on the status of information stored in the selected memory cells of the string. The voltage or current exhibited on the bit line, in accordance with the status of information stored in the selected memory cells, is sensed by a sense amplifier which is called a "sensing circuit".
Various proposals have been made to increase the storage capacity of memory devices without an increase in chip size. One proposal is to provide a technique for storing information of at least two bits per memory cell. In such two-bit memory cells, the status of information stored in each memory cell may be one of "00", "01", "10" and "11". In a multi-bit memory device consisting of memory cells each capable of storing two bits, each memory cell is programmed to have a threshold voltage determined as one of four different values. Accordingly, such a multi-bit memory device can store two bits in the same area as a one-bit memory device while using the number of memory cells corresponding to half the number of memory cells required in the one-bit memory device for that amount of information. Therefore, the chip size is correspondingly reduced for storage of a given amount of information, as compared to the one-bit memory device. As the number of bits stored per memory cell increases, the capacity of the multi-bit memory device increases correspondingly as compared to that of the one-bit memory device.
The most important factor for realizing success in the use of such multi-bit non-volatile memory cells is obtaining an accurate distribution of threshold voltages for memory cells. In other words, where memory cells are desired to have states of "00", "01", "10" and "11", respectively, their threshold voltages should correspond, for example, to: 2.5 V, 1.5 V, 0.5 V and 3 V, respectively. To this end, the use of a verification mode is required. Even in the case of typical one-bit memory devices, a verification operation is successively carried out after the execution of a programming operation or the completion of an erase operation in order to prevent a dispersion of threshold voltages for memory cells caused by an over-progranmming, an over-erase, an insufficient programming, or an insufficient erase. The verification mode checks whether the threshold voltage reaches a target threshold voltage value after the execution of a programming or an erase operation. This verifcation operation is achieved by checking the state of the memory cell in a manner similar to an operation of reading data. Such a technique is disclosed in "Journal of Solid State Circuits" in 1991, pp. 492 to 495. In accordance with this technique, a programming or erase operation is executed again in a verification mode for checking the threshold voltage of a memory cell. The verification of a programming or erasing, executed for memory cells, is achieved by applying signals having the form of voltage to word lines, bit lines and associated lines, thereby sensing current induced on the bit lines in accordance with threshold voltage of the memory cells.
Unfortunately, NAND type memory cell structures have several problems resulting in variation of cell currents due to their structures. For example, in a memory cell structure wherein a plurality of cell strings share one source line, the memory cells have different distances from the associated contacts of the source line, respectively. Such a difference in distance may result in a difference in source line resistance among the memory cells. This causes a difference in the amounts of current flowing through the memory cells. As a result, variation in the threshold voltages of the memory cells occurs. In the case of a multi-bit memory device having a limited level margin, such a difference in cell current, caused by the difference in source line resistance, may cause a problem in that the above-mentioned verification may be impossible. In this case, accordingly, an erroneous operation may be carried out.
Another problem results where a specific bit line is selected, and a capacitive coupling occurs between the selected bit line and a bit line adjacent to the selected bit line. Due to such a capacitive coupling, the bit line voltage of each memory cell varies irrespective of the actual state of the memory cell. As a result, an erroneous operation occurs. For instance, where a memory cell, which is in its ON state, is selected, its bit line voltage decreases. When an "OFF" cell, which is adjacent to an "ON" cell, is selected, it is theoretical that the bit line voltage of the "OFF" cell is high as compared to that of the "ON" cell. Practically, however, the bit line voltage of the "OFF" cell decreases due to a capacitive coupling occurring between adjacent bit lines respectively associated with the "OFF" and "ON" cells. As a result, there is an erroneous verification in that the "OFF" cell is verified as an "ON" cell. Such a phenomenon occurs frequently in a semiconductor memory device which has an increased bit line area for obtaining an increase in memory capacity. This phenomenon occurs more frequently in a semiconductor memory device which has a reduced cell size resulting in a decrease in the distance between adjacent bit lines.
Taking these problems into consideration, various proposals have been made to solve the variations among threshold voltages for memory cells caused by the source line resistance difference among the memory cells and the capacitive coupling phenomenon occurring between adjacent bit lines. One proposal is disclosed in "Symposium on VLSI Circuits Digest of the Technical Papers" in 1995, pp. 69 to 70. In accordance with that technique, string select transistors, each programmed to have two threshold voltages, are arranged beneath bit line contacts, respectively. Bit lines of adjacent strings are connected in common to a bit line contact. Of the two bit lines, one, which is selected in an operation mode, is connected to a sense amplifier called a "page buffer" whereas the other bit line, which is unselected in the operation mode, is coupled to the ground voltage or placed in a float state. Accordingly, the unselected bit line is used as a source line. In this case, it is possible to obtain a very small source line resistance because the source line resistance is based on only the resistance of a metal material forming source lines. By virtue of this very small source line resistance, the unselected bit line adjacent to the selected bit line is maintained at the ground level. As a result, the abovementioned capacitive coupling problem can be substantially solved.
However, the above-mentioned technique involves other problems. For example, in accordance with this technique, the layout of sense amplifiers coupled to bit lines is complex because the metal pitch of the bit lines is short as in typical one-bit NAND memory structures. Such a reduced metal pitch results in a difficulty in the execution of a photolithograpy process required in the manufacture of the desired memory devices. Furthermore, an additional masking process must be carried out to separately fabricate string select transistors, each programmed to have two threshold voltages. The string select transistors fabricated using the additional process have threshold voltages of 2 V or more. As a result, there is a problem in that a reduction in string current, during a read operation, occurs. Moreover, voltage of 1.5 V is applied to the gate of each string select transistor in a programming operation in accordance with the abovementioned technique. As a result, there is a problem in that a program disturbance phenomenon occurs among memory cells which are coupled to the unselected bit line.